Design Verification Engineer
DR-4
Posted: 17/10/2024
- £60000 to £100000 Per: annum
- England, South East, Greater London, London
- FULL_TIME
- testing_qa
Exciting Opportunity for a Verification Engineer!
A leading company in the semiconductor industry is seeking an experienced Verification Engineer with 5+ years of experience and at least 2 years working with UVM (Universal Verification Methodology). This is a unique opportunity for a skilled professional to join a team at the forefront of semiconductor innovation and technology development.
Position Overview: The Verification Engineer will be responsible for ensuring the functionality and performance of complex SoC designs. With a strong background in SystemVerilog and digital verification methodologies, the ideal candidate will take the lead in developing test plans, verifying designs, and working alongside cross-functional teams to drive product success.
Key Responsibilities:
Qualifications:
A leading company in the semiconductor industry is seeking an experienced Verification Engineer with 5+ years of experience and at least 2 years working with UVM (Universal Verification Methodology). This is a unique opportunity for a skilled professional to join a team at the forefront of semiconductor innovation and technology development.
Position Overview: The Verification Engineer will be responsible for ensuring the functionality and performance of complex SoC designs. With a strong background in SystemVerilog and digital verification methodologies, the ideal candidate will take the lead in developing test plans, verifying designs, and working alongside cross-functional teams to drive product success.
Key Responsibilities:
- Lead the verification process of advanced SoC designs using UVM.
- Create, implement, and maintain testbenches and verification environments.
- Collaborate with design, architecture, and firmware teams to identify verification strategies.
- Debug complex RTL designs and ensure verification coverage for design integrity.
Qualifications:
- 5+ years of verification engineering experience.
- At least 2 years of hands-on experience with UVM.
- Expertise in SystemVerilog and testbench architecture.
- Solid understanding of digital design and verification best practices.
- Strong problem-solving skills and the ability to work collaboratively in a team environment.
Daanish Rauf
Consultant